spectre-simulation

Custom VLSI design of a Jitter-Based True Random Number Generator (TRNG) with dynamic selection bit reconfigurability in Cadence Virtuoso. Features dual-VCOs, NLFSR, and 6T SRAM cells.

Full-custom 8-bit Carry Look-Ahead Adder in Cadence Virtuoso 90nm GPDK CMOS. Covers the full IC design flow: transistor schematics, custom layout, Assura DRC signoff (0 errors across 6,970 rules), and 100MHz Spectre transient verification with sub-60ps propagation delay and 20ps edge slews.

Истории автомобилей

Transistor-level design and transient simulation of a 4-bit Ripple Carry Adder using CMOS logic in Cadence Virtuoso (90 nm GPDK).