cla-adder

Full-custom 8-bit Carry Look-Ahead Adder in Cadence Virtuoso 90nm GPDK CMOS. Covers the full IC design flow: transistor schematics, custom layout, Assura DRC signoff (0 errors across 6,970 rules), and 100MHz Spectre transient verification with sub-60ps propagation delay and 20ps edge slews.

CLA gate for Github action workflows.

FPGA labs for EE316 Digital Logic Design using the Basys3 board. Projects include combinational and sequential logic, RCA and CLA adders, datapath and FSM design, registers, timing analysis, and a multi-mode stopwatch with 7-segment display control.

Transistor level 5bit CLA Adder using 180nm CMOS with TSPC DFFs, designing MAGIC layout with optimizations, performing DRC/parasitic extractions, performing NGSpice prelayout & postlayout timing analysis and Verilog/Vivado FPGA based functional validation and prototyping