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…inguish device identity from build match
…P2 readback in any order
…out noisy always-on diagnostics
…tloader target label
… fail-closed PTP runtime UI
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…ithout touching real-time path
…eneric START error
…ithout added polling
…nexistent IDF ioctl
…ers only on START timeout
…ross STOP rollback
…l-closed STOP rollback
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Physical feedback / reproduction
User installed PR #262 through Studio. Firmware pane showed semantic version v0.1.1 and Device ready, hiding 16-digit bundled/observed build identifiers. Time Sync then displayed START FAILED, without the reason in GUI. Old capture report c959... predates new verified install and is not a reliable check of the current board identity. Screenshots alone do not prove PHY/MAC cause.
Root findings
FirmwareManager and DeviceController already have exact expected/observed build IDs; FirmwarePanel displayed neither. Completion step was based on compatible protocol, not exact matching firmware.
Native PTP startup has independently arriving positive role PTP2 and runtime STATUS readbacks. Immediate rejection upon an earlier STOPPED or stale role status is a false negative. Correct behavior must wait for BOTH positive signals within the existing absolute timeout; never fake a lock or skip STOP rollback.
All distinct START errors were collapsed into a generic badge. The ESP32-P4 SOURCE already tracks actual Announce, Sync, Follow_Up, and TX failures but failed to report them at readiness timeout.
Implementation
UI always displays bundled and observed build ID and exact MATCH/MISMATCH, keeps semantic product version, and fixes misleading bootloader target/reinstall labels.
DeviceController retains specific START failure reason plus transaction stage across STOP rollback; native PTP status accepts positive PTP2 and STATUS evidence in either order while remaining bounded/fail-closed.
SOURCE firmware logs concrete 4 counters (and readiness flag) ONLY at failed startup. On failed START, Ethernet diagnostics use the SAME ETH_EVENT FreeRTOS event bit already used by the 4kHz publisher to distinguish link DOWN vs link UP/role runtime invalid, with no polling task, no PHY ioctl and no hot-path changes.
Time Sync shows concise fault text ONLY when needed; Copy diagnostics includes exact stage and detailed logs. No standalone scripts or external bench kit.
Regression structural gates cover exact build UI, bounded runtime proof and single owner Ethernet link diagnostics. PTP SOURCE firmware, Qt, Native Preview, Windows Lifecycle CI must PASS on exact HEAD before artifact.
Not merged to main. Physical PTP TX/relay acceptance is still required; no software-only LOCK claims.