Mersenne-31 FPGA Sumcheck prover with RTL, software cross-checking, synthesis and board validation.
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Updated
Sep 22, 2026 - SystemVerilog
Mersenne-31 FPGA Sumcheck prover with RTL, software cross-checking, synthesis and board validation.
Rust and SystemVerilog tree-based polynomial evaluation over Mersenne-31 with parallel FPGA implementations.
Mersenne-31 kernel-basis experiments and STWO parity/reproducibility artifacts.
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