klayout

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

KLayout Main Sources

A Python library for designing chips (Photonics, Analog, Quantum, MEMS), PCBs, and 3D-printable objects. We aim to make hardware design accessible, intuitive, and fun—empowering everyone to build the future.

SiEPIC EBeam PDK & Library, for SiEPIC-Tools and KLayout

KLayout Python library for integrated quantum circuit design.

gdsfactory plugins

KLayout technology files for Skywater SKY130

Primitives for SKY130 provided by SkyWater.

Sample PDK for Superconducting RF Quantum Circuits

Parametric NEM/MEM relay design with layout generation (KLayout: GDSII), FEM (Ansys/COMSOL), SPICE models, Liberty models, & more

KLayout technology files for FreePDK45

Simple 3D layout viewer for KLayout (Salt package)

Learning Path: RISC-V System-on-Chip (SoC) design, from Register Transfer Level (RTL) to a GDSII layout | Complete VLSI design flow using open-source EDA tools.

Learn, share and collaborate on ASIC design using open tools and technologies

GPU-accelerated GDSII and OASIS layout viewer for VS Code. C++ parser and WebGL2 renderer in WebAssembly, photonic ports, .lyp colors, DRC/LVS markers. Runs on vscode.dev.

Conda + KLayout

Open-source desktop workspace for IC design — schematic capture, analog optimization, SPICE/RTL simulation, synthesis, and digital implementation in one Qt app.

A Python based PCELL generator and Layout generator for adiabatic bragg grating spirals.