A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.
A Python-based CPU simulator featuring a graphical user interface (GUI) to visualize instruction memory, data memory, and register transitions.
A hardware implementation of a MIPS processor written in VHDL
A Python-based CPU simulator featuring a graphical user interface (GUI) to visualize instruction memory, data memory, and register transitions.
VHDL project implementing a single-cycle MIPS processor, including ALU, control units, register file, memories, and full instruction execution, verified via ModelSim simulation (Digital Circuit Design, UNIWA).
Computer Organization and Architecture lab implementations using Verilog, ModelSim
DSH instruction memory plugin: maintain long-term instructions in the DSH settings UI, auto-injected into every subsequent conversation's system prompt.
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