CPU Benchmarks Set
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Jul 25, 2024 - C
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coremark
Here are 17 public repositories matching this topic...
A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)
cpu fpga runtime architecture riscv verilog uart systemverilog hdl microarchitecture branch-prediction coremark rv32i cpu-architecture dhrystone rv32im uart-programming
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Oct 12, 2026 - HTML
5-stage RV32IM RISC-V CPU and FPGA SoC in SystemVerilog, featuring forwarding, hazard control, machine-mode CSR/traps, precise timer interrupts, TCM, UART, GPIO, and FreeRTOS bring-up.
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Oct 24, 2026 - SystemVerilog
Forth language port of CoreMark benchmark (https://www.eembc.org/coremark)
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Sep 25, 2023 - Forth
ArduinoCoreMark is a CPU performance benchmark for Arduino platform based on EEMBC CoreMark.
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Nov 14, 2022 - C
A verified compact 3-stage RV32IMAC RISC-V core with FreeRTOS and Security support
microcontroller fpga embedded-systems riscv freertos vivado systemverilog hardware-designs cpu-cores formal-verification jtag coremark pmp verilator dhrystone pipelined-processors arty-a7 rv32imac riscv-core bspi
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Oct 27, 2026 - SystemVerilog
This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC
asic fpga pipeline processor embedded-systems isa cprogramming risc-v cadence genus coremark rv32i artix7 digitaldesign nexys4ddr dhrystone rv32im innovus systemonchip xilinxvivado
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Aug 8, 2026
5-stage pipelined RV32IMC RISC-V CPU + SoC in Verilog: branch prediction, caches, ISS co-simulation, constrained-random + 100% functional coverage, riscv-formal, ECP5 FPGA timing closure
cpu fpga pipeline cache riscv verilog computer-architecture formal-verification yosys risc-v branch-prediction coremark verilator cocotb ecp5 design-verification riscv-formal
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Oct 1, 2026 - Verilog
A stable version of nexus-am (created by jyy).
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Mar 2, 2022 - C
Performance evaluation of Stage0 (PCGen & Branch Predictor) variants in SHAKTI C-Class RISC-V core RTL — CEG Fabless Internship 2025
rtl bluespec risc-v coremark branch-predictor shakti iit-madras annauniversity c-class riscv-processor
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Apr 13, 2026
Cycle-approximate out-of-order RISC-V CPU simulator with TAGE branch prediction, store-to-load forwarding, and a genetic algorithm for design space exploration using real CoreMark execution.
rust genetic-algorithm design-space-exploration computer-architecture out-of-order risc-v coremark branch-predictor cpu-simulator tage
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May 29, 2026 - Rust
Referencing the CoreMark benchmark method of PerfKitBenchmarker, this is an expanded shell measuring CPU performance with CoreMark, excluding Google Cloud GCE VMs.
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Sep 29, 2026 - Shell
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