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tacticalairfrier/README.md

Chinmay Tupkari

Second-year ECE undergrad @ IIIT Nagpur, building toward VLSI/ASIC/FPGA design roles.

What I've built

Multicycle RISC-V core — Multicycle FSM (Fetch/Decode/Execute/Memory/Writeback) based RV32I core tested against a Self-Written C Golden Model ISS with Byte for Byte memory dump verification, Verified on FPGA ice40up5k.

AES-128 crypto core — Encrypt, InvCipher, and EqInvCipher datapaths, verified against 2000 random test vectors alongside standard NIST test vectors using a self-written C golden model (which caught an InvSBox bug the official vectors missed). Synthesized in Vivado for Basys3 (Artix-7), with ROM inference confirmed for SBox/InvSBox. Hardware bring-up in progress via ILA/VIO.

SPI master/slave controller — Taken through the full OpenLane 2 / Sky130 flow to GDS2. My most complete open-source silicon flow to date.

UART TX/RX — 8E1 framing, 16x oversampling, verified on real ICE40UP5K hardware.

Foundational RTL — Johnson counter, JK-based binary counter with parallel load, universal shift register, traffic light FSM, 16-bit parameterizable ALU. All in Verilog with testbenches, synthesized through Yosys.

Where this is going

Long-term target: A Software Defined Radio using an FPGA ICE40UP5K and a Micro-controller RPi PICO 2 The end goal here being Complete functionality and Compatibility with GNU RADIO aiming at complete PCB of the FPGA, MCU and the ADC controller board.

Long-term target: a security coprocessor SoC — RV32I + AES-128 + SHA-256 + HMAC + CSRNG — with OpenTitan Darjeeling as an architectural reference, aiming at a Sky130 MPW tapeout. Interface strategy: AXI-lite for the SoC, ILA/VIO for FPGA-side bring-up.

Long-term target: an Ethernet controller which adheres the IEEE 802.3 standard along with FPGA demonstration and testing.

Immediate roadmap:

  • Learn More about the SDR along with the required Signals and Systems knowledge and Digital Signal Processing knowledge to attempt each DSP and S&S algorithm inside of gnu-octave.
  • Make a final GNU-OCTAVE script which performs all the functions of the software defined radio which can be used as a Golden Reference Model for the SDR.
  • combine RISCV + AES into a single Processor + Hardware Accelerator combo.

Toolchain

iverilog · GTKWave · Yosys · LibreLane · Sky130 PDK · Vivado

📍 Pune, India — open to VLSI internships

Pinned Loading

  1. AES-128-ENCRYPTION-RTL AES-128-ENCRYPTION-RTL Public

    AES-128 RTL core (Verilog) with encrypt/InvCipher/EqInvCipher, verified against 2000 NIST test vectors.

    Verilog 2

  2. RV32I-CORE RV32I-CORE Public

    A Multicycle riscv-32i implementation along with a golden c model

    Verilog 1

  3. SPI-Interface-Verilog SPI-Interface-Verilog Public

    An implementation of a Serial Peripheral Interface in Verilog using Finite state Machines

    Verilog 1

  4. UART-implementation-in-verilog UART-implementation-in-verilog Public

    A parameterizable, synthesizable RTL implementation of UART protocol in Verilog

    Verilog 2