Electrical engineering at the University of Waterloo. I build across the stack: circuit boards and bare-metal firmware, the software and tools around them, and digital hardware from RTL down to a placed and routed chip layout.
itssaad50@gmail.com · portfolio-saad.com · Looking for Summer 2027 internships in embedded systems, software, and ASIC / digital design
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stm32-sensor-pcb KiCad · bare-metal C · CMSIS · FreeRTOS · Python A custom 4-layer STM32F411 sensor board with register-level firmware (no HAL) and a FreeRTOS pipeline. A BME280 and an OLED share one I²C bus; readings stream as CRC-framed packets to a live Python viewer. 4-layer PCB designed in KiCad · 921600 baud telemetry · CRC-checked framing |
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p1-attention SystemVerilog · cocotb · SymbiYosys · OpenROAD · Vivado A fixed-point attention accelerator (one transformer attention head) with a 4x4 MAC array and an online softmax that never stores the score matrix. Bit-exact against a golden model, formally verified, laid out in sky130 with four SRAM macros. 79.4 MHz sky130 signoff, 0 DRC · 19.9 MAC/cycle · 21.8x faster than optimized C on a RISC-V core · placed and routed, not taped out |
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p2-riscv-soc SystemVerilog · C firmware · UVM · riscv-formal · OpenROAD A 5-stage RV32IM RISC-V SoC with APB peripherals, JTAG debug, RAM self-test, C firmware built with clang, and the attention accelerator on AXI4-Lite in its own clock domain. Every instruction checked against a Python ISS. 119.8 MHz core signoff · riscv-formal 52/52 · 2.27 CoreMark/MHz · full SoC meets timing in Vivado |
Embedded: C, bare-metal ARM (STM32, CMSIS), FreeRTOS, KiCad, UART / I²C / SPI
Software: Python, C++, TypeScript, Git, Linux, Tcl, Perl
Digital hardware: SystemVerilog, VHDL, cocotb, UVM, SVA, SymbiYosys, Yosys, OpenSTA, OpenROAD (sky130), Vivado