ALS-FPGA

An F4PGA-based flow for Xilinx 7-Series FPGAs (xc7) with an approximate-LUT synthesis integrated into the Yosys flow.

Repository layout

als-fpga/
├── tools/
│   ├── f4pga/           # Modified F4PGA 
│   ├── vtr/             
│   └── f4pga-examples/  # Base toolchain installer
├── setup/
│   └── activate.sh      # Sourceable environment activation script
└── README.md

Prerequisites

• Linux x86-64.
• git, wget, xz-utils.
• ~10–15 GB of free disk for the toolchain environment.
• Miniconda is downloaded during installation.

Clone with submodules

The submodules are declared with SSH URLs, so make sure your SSH key is set up with GitHub before cloning.

git clone git@github.com:ECASLab/als-fpga.git
cd als-fpga
 
git submodule update --init --recursive

Install the base toolchain

Go to the f4pga-examples directory:

cd tools/f4pga-examples

Dowload Miniconda installer:

wget https://repo.continuum.io/miniconda/Miniconda3-latest-Linux-x86_64.sh -O conda_installer.sh

Declare dedicated path and family installation:

export F4PGA_INSTALL_DIR=~/opt/f4pga-als
export FPGA_FAM=xc7

Install conda in the path and create the environment:

bash conda_installer.sh -u -b -p $F4PGA_INSTALL_DIR/$FPGA_FAM/conda
source "$F4PGA_INSTALL_DIR/$FPGA_FAM/conda/etc/profile.d/conda.sh"
conda env create -f $FPGA_FAM/environment.yml   

Download architecture definitions and part files:

export F4PGA_PACKAGES='install-xc7 xc7a50t_test xc7a100t_test xc7a200t_test xc7z010_test'
mkdir -p $F4PGA_INSTALL_DIR/$FPGA_FAM
F4PGA_TIMESTAMP='20220920-124259'
F4PGA_HASH='007d1c1'
for PKG in $F4PGA_PACKAGES; do
  wget -qO- https://storage.googleapis.com/symbiflow-arch-defs/artifacts/prod/foss-fpga-tools/symbiflow-arch-defs/continuous/install/${F4PGA_TIMESTAMP}/symbiflow-arch-defs-${PKG}-${F4PGA_HASH}.tar.xz | tar -xJC $F4PGA_INSTALL_DIR/${FPGA_FAM}
done

Override with the modified F4PGA

With the environment active, uninstall the upstream f4pga and install this repo's version in editable mode:

conda activate xc7
pip uninstall -y f4pga
pip install -e tools/f4pga/f4pga    # adjust the path depending on where you are

You should see it uninstall f4pga 0.0.0+e1cd038f0 (upstream) and install f4pga 0.0.0+8bfab9dc.

Install VTR

Go to the VTR directory:

cd tools/vtr

Install system dependencies:

sudo ./install_apt_packages.sh

Install VTR:

make -j"$(nproc)"

ACE's binary lands at tools/vtr/build/ace2/ace. Create a symlink under a different name on the local binary directory:

mkdir -p ~/.local/bin
ln -sf "$PWD/build/ace2/ace" ~/.local/bin/vtr-ace

Environment SETUP

For daily work, this repo includes setup/activate.sh, which activates the conda environment, checks that the modified f4pga is the one in use, and makes sure vtr-ace is on PATH, all in one command, with a readable summary.

It must be sourced, not executed, since it needs to change PATH and activate conda in your current shell:

source setup/activate.sh

Running a synthesis sweep

Once the environment is active, scripts/auto_sweep.py runs the approximate-LUT flow across a baseline and a list of error thresholds, collects LUTs/timing/error/power metrics into a table and a CSV. It uses scripts/run_synth.sh in the background, so no separate setup is needed beyond what's already done above.

Run the sweep against your Verilog design, giving it the source file, the top module name, and the thresholds to try:

./scripts/auto_sweep.py -v path/to/design.v -t TopModuleName --thresholds 0.00005,0.0001,0.0005 --metric wber --power -o results.csv

• --metric accepts ber or wber (default: wber).
• Add --power to also run the ACE/VPR power-estimation step for each config.
• Add -o results.csv to change the output CSV path (default: sweep_results.csv in the current directory).

For a single run instead of a sweep, or for options auto_sweep.py doesn't expose, call scripts/run_synth.sh directly — run ./scripts/run_synth.sh -h for its full flag list.